1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to an SRAM (static random access memory).
2. Description of the Background Art
In relation to a MOSFET (metal oxide silicon field-effect transistor) employing an SOI (silicon on insulator) substrate, a DTMOSFET (dynamic threshold voltage MOSFET, hereinafter abbreviated as “DTMOS”) is proposed as means for increasing the operating speed and improving the current driving capability (refer to Japanese Patent Application Laying-Open Gazette No. 2001-77368, pp. 4 to 6, FIG. 3, for example).
The SOI substrate has a multilayer structure obtained by stacking a silicon substrate, a buried oxide film (BOX) layer and a silicon layer (SOI layer) in this order. In the DTMOS, a gate electrode having a gate oxide film on the lower surface thereof is selectively formed on the SOI layer. Further, source/drain regions paired through a body region located under the gate electrode are formed in the SOI layer. The feature of the DTMOS resides in that the gate electrode and the body region are electrically connected with each other.
When the gate electrode goes high to turn on the transistor in the DTMOS, a body potential also goes high. Then, the operating threshold voltage of the transistor is reduced so that a larger quantity of current can be fed as compared with a general MOSFET employing an SOI substrate (in other words, the current driving capability is improved).
In general, a gate electrode of a transistor has an electrode part provided on an active region and a pad part provided on an element isolation insulating film connected thereto. As disclosed in Japanese Patent Application Laying-Open Gazette No. 2001-77368, a contact reaching the SOI layer provided under the element isolation insulating film is formed in the pad part of the gate electrode of the DTMOS. The SOI layer provided under the element isolation insulating film is joined to the body region provided under the gate electrode and has the same conductivity type as the body region. In other words, the gate electrode and the body region of the DTMOS are electrically connected with each other through the aforementioned contact and the SOI layer provided under the element isolation insulating film.
However, the DTMOS has a larger element forming area as compared with a general MOSFET due to the contact formed in the pad part of the gate electrode for connecting the gate electrode and the body region with each other. Therefore, it is difficult to apply the DTMOS to a device required to form a large number of transistors in a small area on a semiconductor substrate.
An SRAM can be listed an example of such devices. If the DTMOS is applied to each of transistors (memory transistors) constituting memory cells of the SRAM, the operating threshold voltage of each SRAM cell is so reduced that the operating speed performance can be improved. In general, each SRAM cell has four transistors and two loads. Following recent reduction of driving voltages for semiconductor devices, however, SRAM cells each constituted of six transistors including two access transistors, two driver transistors and two load transistors in total have been increasingly mainstreamed. Therefore, it is further difficult to apply the DTMOS to the SRAM.
In the DTMOS, as a gate electrode is connected to a body region, the P-N junction between the body region and a source and a drain may be forward biased during increase of the potential of the gate electrode, thereby causing flow of a leakage current therethrough. Thus, application of the DTMOS to an SRAM cell may increase the power consumption of an SRAM.